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| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 m38277m8mxxxfp seg 9 p3 1 /seg 19 p3 0 /seg 18 p3 2 /seg 20 p3 3 /seg 21 p3 4 /seg 22 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 p3 5 /seg 23 p3 6 /seg 24 p3 7 /seg 25 p0 0 /seg 26 p0 1 /seg 27 p0 2 /seg 28 p0 3 /seg 29 p0 4 /seg 30 p0 5 /seg 31 p0 6 /seg 32 p0 7 /seg 33 p1 0 /seg 34 p1 1 /seg 35 p1 2 /seg 36 p1 3 /seg 37 p1 4 /seg 38 p1 5 /seg 39 c 1 v l1 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 2 /s clk21 /an 2 p6 1 /s out2 /an 1 p6 0 /s in2 /an 0 p5 7 /da 2 p5 6 /da 1 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /rtp 1 p5 2 /rtp 0 p5 1 /pwm 1 p5 0 /pwm 0 p4 6 /s clk1 p4 5 /t x d p4 4 /r x d p4 3 / f /t out p4 2 /int 2 p4 1 /int 1 p4 0 /adt p7 7 p7 6 p7 5 p7 4 c 2 v l2 v l3 com 0 com 1 com 2 v ref av ss v cc seg 8 seg 0 seg 1 seg 2 seg 4 seg 5 seg 6 seg 7 seg 3 p7 2 p7 3 p7 1 p7 0 /int 0 x cin x cout x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 1 p1 6 p2 2 p2 0 p1 7 reset seg 16 seg 17 com 3 p4 7 /s rdy1 p6 3 /s clk22 /an 3 description the 3827 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3827 group has the lcd drive control circuit, the a-d/d-a converter, the uart, and the pwm as additional functions. the various microcomputers in the 3827 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3827 group, re- fer to the section on group expansion. features l basic machine-language instructions ...................................... 71 l the minimum instruction execution time ........................... 0.5 m s (at 8mhz oscillation frequency) l memory size rom ................................................................. 4 k to 60 k bytes ram ................................................................. 192 to 2048 bytes l programmable input/output ports ............................................ 55 l output port ................................................................................. 8 l input port .................................................................................... 1 l interrupts ................................................. 17 sources, 16 vectors (includes key input interrupt) l timers ........................................................... 8-bit 5 3, 16-bit 5 2 l serial i/o1 .................... 8-bit 5 1 (uart or clock-synchronized) l serial i/o2 ...................................8-bit 5 1 (clock-synchronized) l pwm output .................................................................... 8-bit 5 1 l a-d converter ............................................... 10-bit 5 8 channels l d-a converter ................................................. 8-bit 5 2 channels l lcd drive control circuit bias ................................................................................... 1/2, 1/3 duty ........................................................................... 1/2, 1/3, 1/4 common output .......................................................................... 4 segment output ........................................................................ 40 l 2 clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) l watchdog timer ............................................................ 14-bit 5 1 l power source voltage ................................................ 2.2 to 5.5 v l power dissipation in high-speed mode .......................................................... 40 mw (at 8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 60 m w (at 32 khz oscillation frequency, at 3 v power source voltage) l operating temperature range ................................... C 20 to 85 c applications camera, wireless phone, etc. 3827 group mitsubishi microcomputers single-chip 8-bit cmos microcomputer fig. 1 m38277m8mxxxfp pin configuration pin configuration (top view) package type : 100p6s-a (100-pin plastic-molded qfp)
2 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers m38277m8mxxxgp m38277m8mxxxhp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p5 0 /pwm 0 p4 7 /s rdy1 p5 7 /da 2 p4 6 /s clk1 p4 4 /r x d p4 3 / f /t out p4 2 /int 2 p5 4 /cntr 0 p5 2 /rtp 0 p5 3 /rtp 1 p5 1 /pwm 1 p5 5 /cntr 1 p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /s clk22 /an 3 p6 2 /s clk21 /an 2 p6 1 /s out2 /an 1 p6 0 /s in2 /an 0 p4 5 / t x d p4 1 /int 1 p4 0 /adt p7 7 31 32 33 34 35 36 37 38 39 40 41 42 49 50 43 44 45 46 47 48 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 59 58 57 60 56 54 53 52 55 51 seg 13 seg 14 seg 15 seg 16 seg 17 p3 0 /seg 18 p3 1 /seg 19 p3 2 /seg 20 p3 3 /seg 21 p3 4 /seg 22 p3 5 /seg 23 p3 6 /seg 24 p3 7 /seg 25 p0 1 /seg 27 p0 2 /seg 28 p0 3 /seg 29 p0 4 /seg 30 p0 5 /seg 31 p0 6 /seg 32 p0 7 /seg 33 p1 2 /seg 36 p1 3 /seg 37 p0 0 /seg 26 p1 0 /seg 34 p1 1 /seg 35 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 10 0 26 27 28 29 30 p7 0 /int 0 x in x out v ss p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 reset x cout x cin p1 7 p1 6 p7 1 p7 2 p7 3 p7 4 p7 5 p7 6 p1 5 /seg 39 p1 4 /seg 38 76 77 78 79 80 v cc seg 6 seg 7 seg 5 seg 3 seg 4 seg 2 seg 1 seg 0 v ref av ss com 2 com 3 com 1 com 0 v l3 seg 8 seg 9 v l2 c 2 c 1 v l1 seg 10 seg 11 seg 12 p5 6 /da 1 package type : gp........ 100p6q-a (100-pin plastic-molded lqfp) package type : hp ........ 100pfb-a (100-pin plastic-molded tqfp) pin configuration (top view) fig. 2 m38277m8mxxxgp/m38277m8mxxxhp pin configuration 3 single-chip 8-bit cmos microcomputer mitsubishi micr ocomputers 3827 gr oup functional block dia gram fig. 3 functional block diagram key input/key-on wake-up interrupt int 1, int 2 cntr 0 ,cntr 1 da 1 da 2 t out int 0 adt data bus c p u a x y s pc h pc l ps reset v cc v ss reset input ( 5 v ) ( 0 v ) r o m r a m lcd display ram (20 bytes) i/o port p5 p4(8) i/o port p4 i/o port p2 p2(8) i/o port p0 p0(8) i/o port p1 p1(8) p6(8) i/o port p7 p7(8) output port p3 p3(8) i/o port p6 p5(8) sub-clock input sub-clock output x cin x cout clock generating circuit x in out x main clock input main clock output cout x x cin sub-clock output sub-clock input si/o1 (8) v ref av ss a-d converter (10) timer x(16) timer y(16) timer 1(8) timer 2(8) timer 3(8) lcd drive control circuit v l1 c 1 c 2 v l2 v l3 com 0 com 1 com 2 com 3 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 f x cin cout x si/o2(8) watchdog timer reset pwm(8) f real time port function d-a2 d-a1 4 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers pin description table 1 pin description (1) v cc , v ss function pin name function except a port function ?lcd segment output pins power source ?apply voltage of 2.2 v to 5.5 v to v cc , and 0 v to v ss . v ref av ss reset x in x out v l1 Cv l3 c 1 , c 2 com 0 Ccom 3 seg 0 Cseg 17 p0 0 /seg 26 C p0 7 /seg 33 p1 0 /seg 34 C p1 5 /seg 39 p1 6 , p1 7 p2 0 C p2 7 p3 0 /seg 18 C p3 7 /seg 25 analog refer- ence voltage analog power source reset input clock input clock output lcd power source charge-pump capacitor pin common output segment output i/o port p0 i/o port p1 i/o port p2 output port p3 ?reference voltage input pin for a-d converter and d-a converter. ?gnd input pin for a-d converter and d-a converter. ?connect to v ss . ?reset input pin for active l. ?input and output pins for the main clock generating circuit. ?connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?input 0 v l1 v l2 v l3 v cc voltage. ?input 0 C v l3 voltage to lcd. ?external capacitor pins for a voltage multiplier (3 times) of lcd contorl. ?lcd common output pins. ?com 2 and com 3 are not used at 1/2 duty ratio. ?com 3 is not used at 1/3 duty ratio. ?lcd segment output pins. ?8-bit output port. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up control is enabled. ?i/o direction register allows each port to be individually programmed as either input or output. ?6-bit output port with same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up control is enabled. ?i/o direction register allows each 6-bit pin to be pro- grammed as either input or output. ?2-bit i/o port. ?cmos compatible input level. ?cmos 3-state output structure. ?i/o direction register allows each pin to be individually programmed as either input or output. ?pull-up control is enabled. ?8-bit i/o port with same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up control is enabled. ?8-bit output port with same function as port p0. ?cmos 3-state output structure. ?port output control is enabled. ?key input (key-on wake-up) interrupt input pins ?lcd segment output pins 5 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group table 2 pin description (2) function pin name function except a port function ?a-d trigger input pin ?interrupt input pin p4 0 /adt p4 1 /int 1 , p4 2 /int 2 p4 3 / f /t out p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /pwm 0 , p5 1 /pwm 1 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /da 1 , p5 7 /da 2 p6 0 /an 0 /s in2, p6 1 /an 1 /s out2, p6 2 /an 2 /s clk21, p6 3 /an 3 /s clk22 p6 4 /an 4 C p6 7 /an 7 p7 0 /int 0 p7 1 Cp7 7 x cout x cin i/o port p4 i/o port p5 i/o port p6 input port p7 i/o port p7 sub-clock output sub-clock input ?1-bit i/o port with same function as p1 6 and p1 7 . ?cmos compatible input level. ?cmos 3-state output structure. ?7-bit i/o port with same function as p1 6 and p1 7 . ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up control is enabled. ?8-bit i/o port with same function as p1 6 and p1 7 . ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up control is enabled. ?8-bit i/o port with same function as p1 6 and p1 7 . ?cmos compatible input level. ?cmos 3-state output structure. ?pull-up control is enabled. ?1-bit i/o port. ?cmos compatible input level. ?7-bit i/o port with same function as p1 6 and p1 7 . ?cmos compatible input level. ?n-channel open-drain output structure. ?sub-clock generating circuit i/o pins. (connect a resonator. external clock cannot be used.) ?interrupt input pins ? f clock output pin ?timer 2 output pin ?serial i/o1 i/o pins ?pwm function pins ?real time port function pins ?timer x, y function pins ?d-a conversion output pins ?a-d conversion input pins ?serial i/o2 i/o pins ?a-d conversion input pins ?interrupt input pin 6 single-chip 8-bit cmos microcomputer 3827 gr oup mitsubishi micr ocomputers m3827 7 m 8 m xxx hp product rom/prom size 1 2 3 4 5 6 7 8 9 a b c d e f : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : eprom or one time prom version ram size 0 1 2 3 4 5 6 7 8 9 : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes rom number omitted in some types. normally, using hyphen when electrical characteristic, or division of quality identification code using alphanumeric character. e : standard m : low power source version package type fp hp gp fs : 100p6s-a package : 100pfb-a package : 100p6q-a package : 100d0 package p ar t numbering fig. 4 part numbering 7 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group group expansion mitsubishi plans to expand the 3827 group as follows: memory type support for mask rom, one time prom, and eprom versions memory size rom/prom size ................................................. 4 k to 60 k bytes ram size ............................................................ 192 to 2048 bytes package 100pfb-a ................................ 0.4 mm-pitch plastic molded tqfp 100p6q-a ................................ 0.5 mm-pitch plastic molded lqfp 100p6s-a ................................ 0.65 mm-pitch plastic molded qfp 100d0 ..................... window type ceramic lcc (eprom version) currently supported products are listed below. memory expansion plan remarks package product as of may 1998 ram size (bytes) 32768 (32638) (p) rom size (bytes) rom size for user in ( ) 61440 (61310) fig. 5 memory expansion plan table 3 list of supported products m38277m8mxxxfp m38277m8mxxxhp m38277m8mxxxgp m38279ef-xxxfp m38279effp m38279ef-xxxhp m38279efhp m38279ef-xxxgp m38279efgp m38279effs 1024 2048 100p6s-a 100pfb-a 100p6q-a 100p6s-a 100p6s-a 100pfb-a 100pfb-a 100p6q-a 100p6q-a 100d0 mask rom version mask rom version mask rom version one time prom version one time prom version (blank) one time prom version one time prom version (blank) one time prom version one time prom version (blank) eprom version note: products under development or planning: the development schedule and specifications may be revised without notice. rom size (bytes) 32k 28k 24k 20k 16k 12k 8k 4k 256 384 512 640 768 896 1024 192 ram size (bytes) 2048 1920 1152 1280 1408 1536 1664 1792 36k 40k 44k 48k 52k 56k 60k under development m38277m8m m38278mcm planning m38279ef under development 8 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers not available processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : 1 1 : stack page selection bit 0 : 0 page 1 : 1 page not used (returns ??when read) (do not write ??to this bit.) port x c switch bit 0 : stop oscillating 1 : x cin , x cout main clock ( x in -x out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bit 0 : x in /2 (high-speed mode) 1 : x in /8 (middle-speed mode) internal system clock selection bit 0 : x in -x out selected (middle-/high-speed mode) 1 : x cin -x cout selected (low-speed mode) cpu mode register (cpum (cm) : address 003b 16 ) b7 b0 functional description central processing unit (cpu) the 3827 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 6 structure of cpu mode register 9 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 7 memory map diagram 192 256 384 512 640 768 896 1024 1536 2048 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 ram area ram size (bytes) address xxxx 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 rom area rom size (bytes) address yyyy 16 address zzzz 16 0100 16 0000 16 0040 16 0840 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram rom 0054 16 reserved area sfr area not used interrupt vector area reserved rom area (128 bytes) zero page special page lcd display ram area reserved rom area 10 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 8 memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p1 (p1) port p1 output control register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) pull register a (pulla) pull register b (pullb) transmit/receive buffer register(tb/rb) port p0 direction register (p0d) port p3 output control register (p3c) key input control register (kic) serial i/o2 control register (sio2con) reserved area serial i/o2 register (sio2) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 interrupt control register 2(icon2) timer 3 (t3) timer x mode register (txm) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1(ireq1) interrupt request register 2(ireq2) interrupt control register 1(icon1) timer x (low) (txl) timer y (low) (tyl) timer 1 (t1) timer 2 (t2) timer x (high) (txh) timer y (high) (tyh) timer y mode register (tym) timer 123 mode register (t123m) t out / f output control register (ckcon) segment output enable register (seg) lcd mode register (lm) a-d control register (adcon) a-d control register (low-order) (adl) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) a-d control register (high-order) (adh) d-a1 conversion register (da1) d-a2 conversion register (da2) d-a control register (dacon) watchdog timer control register (wdtcon) 11 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group i/o ports direction registers the i/o ports have direction registers which determine the input/ output direction of each individual pin. (p0 0 Cp0 7 and p1 0 Cp1 5 use bit 0 of port p0, p1 direction registers respectively.) when 1 is written to that bit, that pin becomes an output pin. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating and the value of that pin can be read. if a pin set to input is written to, only the port output latch is written to and the pin re- mains floating. port p3 output control register bit 0 of the port p3 output control register (address 0007 16 ) en- ables control of the output of ports p3 0 to p3 7 . when the bit is set to 1, the port output function is valid. when resetting, bit 0 of the port p3 output control register is set to 0 (the port output function is invalid.) and ports p3 0 to p3 7 are pulled up. pull-up control by setting the pull register a (address 0016 16 ) or the pull reg- ister b (address 0017 16 ), ports p0 to p6 can control pull-up with a program. however, the contents of pull register a and pull register b do not affect ports programmed as the output ports. the pull register a setting is invalid for pins set to segment out- put on the segment output enable register. fig. 9 structure of pull register a and pull register b p0 0 , p 0 1 pull-up p0 2 , p0 3 pull-up p0 4 ?0 7 pull-up p1 0 ?1 3 pull-up p1 4 , p1 5 pull-up p1 6 , p1 7 pull-up p2 0 ?2 3 pull-up p2 4 ?2 7 pull-up pull register a (pulla : address 0016 16 ) b7 b0 p4 1 ?4 3 pull-up p4 4 ?4 7 pull-up p5 0 ?5 3 pull-up p5 4 ?5 7 pull-up p6 0 ?6 3 pull-up p6 4 ?6 7 pull-up not used (return ??when read) 0 : no pull-up 1 : pull-up pull register b (pullb : address 0017 16 ) b7 b0 note : the contents of pull register a and pull register b do not affect ports programmed as the output port. 12 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers pwm output da 2 output da 1 output a-d v ref input diagram no. related sfrs input/output name pin non-port function i/o format table 4 list of i/o port function (1) p0 0 /seg 26 C p0 7 /seg 33 p1 0 /seg 34 C p1 5 /seg 39 p1 6 , p1 7 p2 0 Cp2 7 p3 0 /seg 18 C p3 7 /seg 25 p4 0 /adt p4 1 /int 1 , p4 2 /int 2 p4 3 / f /t out p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /pwm 0 , p5 1 /pwm 1 p5 2 /rtp 0 , p5 3 /rtp 1 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /da 1 p5 7 /da 2 por t p0 por t p1 port p2 por t p3 por t p4 port p5 input/output, byte unit input/output, 6-bit unit input/output, individual bits input/output, individual bits output input/output, individual bits input/output, individual bits cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output cmos 3-state output cmos compatible input level n-channel open-drain output cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output lcd segment output lcd segment output key input (key-on wake-up) interrupt input lcd segment output a-d trigger input external interrupt input external interrupt input timer output f output serial i/o1 function i/o real time port function output timer x function i/o timer y function input pull register a segment output enable register pull register a segment output enable register pull register a pull register a interrupt control register2 key input control register pull register a segment output enable register p3 output enable register a-d control register interrupt edge selection register pull register b interrupt edge selection register pull register b timer 123 mode register t out / f output control register pull register b serial i/o1 control register serial i/o1 status register uart control register pull register b pwm control register pull register b timer x mode register pull register b timer x mode register pull register b timer y mode register pull register b d-a control register a-d control register pull register b d-a control register (1) (2) (1) (2) (4) (4) (3) (13) (4) (12) (5) (6) (7) (8) (10) (9) (11) (14) (15) (15) 13 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group pin name i/o format non-port function related sfr s diagram no. input/output notes1: how to use double-function ports as function i/o ports, refer to the applicable sections. 2: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate po- tential, a current will flow v cc to v ss through the input-stage gate. table 5 list of i/o port function (2) p6 0 /s in2 /an 0 p6 1 /s out2 / an 1 p6 2 /s clk21 / an 2 p6 3 /s clk22 / an 3 p6 4 /an 4 C p6 7 /an 7 p7 0 /int 0 p7 1 Cp7 7 com 0 Ccom 3 seg 0 Cseg 17 por t p6 por t p7 common segment input/ output, individnal bits input input/ output, individnal bits output output cmos compatible input level cmos 3-state output cmos compatible input level cmos compatible input level n-channel open-drain output lcd common output lcd segment output a-d conversion input serial i/o2 function i/o a-d conversion input external interrupt input a-d control register serial i/o2 control register a-d control register interrupt edge selection register lcd mode register (17) (18) (19) (20) (16) (23) (13) (21) (22) 14 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 10 port block diagram (1) (5) port p4 4 (4) ports p1 6 , p1 7 , p2, p4 1 , p4 2 except p1 6 , p1 7 data bus direction register port latch pull-up control key input interrupt input int 1 , int 2 interrupt input serial i/o1 enable bit reception enable bit serial i/o1 input port latch pull-up control (1) ports p0 1 ?0 7 , p1 1 ?1 5 port direction register data bus port latch segment data lcd drive timing port/segment segment/port segment port pull-up v l1 /v ss v l2 /v l3 /v cc interface logic level shift circuit port direction register (2) ports p0 0 , p1 0 port direction register data bus port latch segment data lcd drive timing port/segment segment/port segment port pull-up v l1 /v ss v l2 /v l3 /v cc interface logic level shift circuit direction register (3) port p3 output control data bus port latch segment data lcd drive timing port/segment segment/port segment port pull-up v l1 /v ss v l2 /v l3 /v cc interface logic level shift circuit data bus direction register 15 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group fig. 11 port block diagram (2) (6) port p4 5 (7) port p4 6 (8) port p4 7 data bus serial i/o1 enable bit transmission enable bit serial i/o1 output p4 5 /txd p-channel output disable bit port latch direction register pull-up control serial i/o1 ready output data bus port latch serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit direction register pull-up control (9) ports p5 2 , p5 3 data bus port latch real time control bit real time port data direction register pull-up control serial i/o1 clock selection bit data bus serial i/o1 clock outupt serial i/o1 clock input serial i/o1 mode selection bit serial i/o1 enable bit port latch direction register serial i/o1 enable bit pull-up control (10) ports p5 0 ,p5 1 data bus port latch pwm function enable bit pwm output direction register pull-up control (11) port p5 4 port latch data bus pulse output mode timer output cntr 0 interrupt input direction register pull-up control 16 single-chip 8-bit cmos microcomputer 3827 gr oup mitsubishi micr ocomputers fig. 12 port block diagram (3) (12) port p4 3 port latch data bus t out / f output control timer output direction register pull-up control f output t out / f selection bit (13) ports p4 0 , p7 1 ep7 7 port latch data bus direction register (14) port p5 5 data bus direction register port latch pull-up control cntr 1 interrupt input (15) ports p5 6 , p5 7 data bus direction register port latch pull-up control d-a conversion output a-d trigger input except p7 1 to p7 7 (16) ports p6 4 ep6 7 analog input pin selection bit a-d conversion input data bus port latch direction register pull-up control (17) port p6 0 data bus port latch direction register pull-up control serial i/o2 input d-a 1 , d-a 2 output enable bit v ref input switch v ref input selection bit except p5 7 a-d conversion input analog input pin selection bit 17 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group fig. 13 port block diagram (4) (18) port p6 1 (19) port p6 2 (20) port p6 3 data bus serial i/o2 output port latch serial i/o2 transmit completion signal synchronous clock selection bit serial i/o2 port selection bit direction register pull-up control analog input pin selection bit a-d conversion input p6 1 /s out2 p-channel output disable bit (21) com 0 ?om 3 (22) seg 0 ?eg 17 v l3 v l2 v l1 v ss v l2 /v l3 v l1 /v ss the gate input signal of each transistor is controlled by the lcd duty ratio and the bias value. the voltage applied to the sources of p-channel and n-channel transistors is the controlled voltage by the bias value. (23) port p7 0 data bus port latch direction register int 0 input synchronous clock selection bit data bus serial i/o2 clock output serial i/o2 clock input port latch direction register data bus port latch direction register synchronous clock selection bit serial i/o2 port selection bit synchronous clock output pin selection bit pull-up control synchronous clock output pin selection bit serial i/o2 port selection bit pull-up control analog input pin selection bit a-d conversion input serial i/o2 clock output analog input pin selection bit a-d conversion input 18 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers interrupts interrupts occur by seventeen sources: seven external, nine inter- nal, and one software. interrupt control each interrupt except the brk instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. an interrupt occurs if the correspond- ing interrupt request and enable bits are 1 and the interrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all inter- rupts except the brk instruction interrupt and reset. if several interrupts requests occurs at the same time the interrupt with high- est priority is accepted first. interrupt operation upon acceptance of an interrupt the following operations are auto- matically performed: 1. the contents of the program counter and processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vec- tor table into the program counter. n notes when the active edge of an external interrupt (int 0 Cint 2 , cntr 0 , cntr 1 ) is set or when switching interrupt sources of adt/a-d conversion interrupt, the corresponding interrupt request bit may also be set. therefore, take following sequence: (1) disable the external interrupt which is selected. (2) change the active edge in interrupt edge selection register (timer xy mode register when using cntr 0 , cntr 1 ) (3) clear the set interrupt request bit to 0. (4) enable the external interrupt which is selected. notes1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. table 6 interrupt vector addresses and priority remarks interrupt request generating conditions at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at completion of serial i/o1 data reception at completion of serial i/o1 transmit shift or when transmis- sion buffer is empty interrupt source low high priority vector addresses (note 1) reset (note 2) int 0 int 1 serial i/o1 reception serial i/o1 transmission timer x timer y timer 2 timer 3 cntr 0 cntr 1 timer 1 int 2 serial i/o2 key input (key-on wake-up) adt a-d conversion brk instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 2 input at completion of serial i/o2 data transmission or reception at falling of conjunction of input level for port p2 (at input mode) at falling of adt input at completion of a-d conversion at brk instruction execution non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o1 is selected valid when serial i/o1 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid when serial i/o2 is selected external interrupt (valid when an l level is applied) valid when adt interrupt is se- lected external interrupt (valid at falling) valid when a-d interrupt is se- lected non-maskable software interrupt 19 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group fig. 14 interrupt control fig. 15 structure of interrupt-related registers b7 b0 interrupt edge selection register int 0 interrupt edge selection bit int 1 interrupt edge selection bit int 2 interrupt edge selection bit int 3 interrupt edge selection bit not used (return ??when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 cntr 0 interrupt request bit cntr 1 interrupt request bit timer 1 interrupt request bit int 2 interrupt request bit serial i/o2 interrupt request bit key input interrupt request bit adt/ad conversion interrupt request bit not used (returns ??when read) (ireq2 : address 003d 16 ) interrupt control register 2 cntr 0 interrupt enable bit cntr 1 interrupt enable bit timer 1 interrupt enable bit int 2 interrupt enable bit serial i/o2 interrupt enable bit key input interrupt enable bit adt/ad conversion interrupt enable bit not used (returns ??when read) (do not write ??to this bit.) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active b7 b0 b7 b0 b7 b0 b7 b0 interrupt request bit interrupt enable bit interrupt disable flag (i) brk instruction reset interrupt request 20 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers key input interrupt (key-on wake-up) a key-on wake up interrupt request is generated by applying l level to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0. an example of using a key input interrupt is shown in figure 16, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 Cp2 3 . fig. 16 connection example when using key input interrupt and port p2 block diagram ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] port p2 0 latch port p2 0 direction register = ? port p2 1 latch port p2 1 direction register = ? port p2 2 latch port p2 2 direction register = ? port p2 3 latch port p2 3 direction register = ? port p2 4 latch port p2 4 direction register = ? port p2 5 latch port p2 5 direction register = ? port p2 6 latch port p2 7 latch port p2 7 direction register = ? port p2 0 input port p2 1 input port p2 2 input port p2 3 input port p2 4 output port p2 5 output port p2 6 output port p2 7 output pulla register bit 2 = ? port p2 input reading circuit key input interrupt request port pxx ??level output ] p-channel transistor for pull-up ]] cmos output buffer key input control register = ? key input control register = ? key input control register = ? key input control register = ? key input control register = ? key input control register = ? key input control register = ? port p2 6 direction register = ? key input control register = ? 21 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group cntr 0 active edge switch bit timer 1 count source selection bit real time port control bit ?? ? p5 5 /cntr 1 ? f(x in )/16 (f(x cin ) 5 16 in f = x cin divided by 2) cntr 1 active edge switch bit ?0 timer y stop control bit falling edge detection period measurement mode timer y interrupt request pulse width hl continuously measurement mode rising edge detection ?0??1??1 timer y operating mode bit timer x interrupt request timer x mode register write signal p5 4 /cntr 0 q q t s p5 4 direction register pulse output mode p5 4 latch timer x stop control bit ? ? timer x write control bit q d latch q d latch ? ? ? ?0 timer x operat- ing mode bits ?0??1??1 f(x in )/16 (f(x in )/16 in low-speed mode ] ) pulse width measurement mode cntr 0 active edge switch bit pulse output mode q q t s ? p4 3 direction register p4 3 latch ? t out output active edge switch bit timer 2 write control bit ? ? t out output control bit ? p4 3 / f /t out x cin timer 3 count source selection bit ? ? timer 2 interrupt request timer 3 interrupt request timer 2 count source selection bit timer 1 interrupt request data bus f(x in )/16 (f(x cin )/16 in f = x cin divided by 2) f(x in )/16 (f(x cin ) 5 16 in f =x cin divided by 2) f(x in )/16(f(x cin )/16 in low-speed mode ] ) cntr 0 interrupt request cntr 1 interrupt request timer y operating mode bit ?0??1??0 ?1 real time port control bit ? p5 2 latch real time port control bit ? p5 3 latch timer y (low) (8) timer y (high) (8) timer 3 latch (8) timer 3 (8) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) timer x (low) (8) timer x (high) (8) timer x (low) latch (8) timer x (high) latch (8) timer y (low) latch (8) timer y (high) latch (8) t out output control bit ? ? ? p5 2 p5 3 p5 2 direction register p5 3 direction register p5 2 data for real time port p5 3 data for real time port timers the 3827 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit cor- responding to that timer is set to 1. read and write operation on 16-bit timer must be performed for both high and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. fig. 17 timer block diagram 22 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers timer x mode register (txm : address 0027 16 ) timer x write control bit 0 : write value in latch and counter 1 : write value in latch only real time port control bit 0 : real time port function invalid 1 : real time port function valid p5 2 data for real time port p5 3 data for real time port timer x operating mode bits b5 b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 0 active edge switch bit 0 : count at rising edge in event counter mode start from ??output in pulse output mode measure ??pulse width in pulse width measurement mode falling edge active for cntr 0 interrupt 1 : count at falling edge in event counter mode start from ??output in pulse output mode measure ??pulse width in pulse width measurement mode rising edge active for cntr 0 interrupt timer x stop control bit 0 : count start 1 : count stop b7 b0 timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write and the real time port by setting the timer x mode register. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 0 pin to input. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 0 pin to input. (4) pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in low-speed mode). if cntr 0 active edge switch bit is 0, the timer counts while the in- put signal of cntr 0 pin is at h. if it is 1, the timer counts while the input signal of cntr 0 pin is at l. when using a timer in this mode, set the port shared with tha cntr 0 pin to input. l timer x write control if the timer x write control bit is 0, when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. if the timer x write control bit is 1, when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. n note on cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. l real time port control while the real time port function is valid, data for the real time port are output from ports p5 2 and p5 3 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1, data are output without the timer x.) when the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer x. before using this function, set the corresponding port direction registers to output mode. fig. 18 structure of timer x mode register 23 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in low-speed mode). (2) period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when using a timer in this mode, set the port shared with the cntr 1 pin to input. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. when using a timer in this mode, set the port shared with the cntr 1 pin to input. (4) pulse width hl continuously measurement mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the port shared with the cntr 1 pin to input. n note on cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 19 structure of timer y mode register timer y mode register (tym : address 0028 16 ) b7 b0 not used (return ??when read) timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge to falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer y stop control bit 0 : count start 1 : count stop 24 single-chip 8-bit cmos microcomputer 3827 gr oup mitsubishi micr ocomputers timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers . the count source f or each timer can be selected by timer 123 mode register . the timer latch v alue is not aff ected b y a change of the count source . how- ev er , because changing the count source ma y cause an inadv er tent count do wn of the timer . theref ore , re wr ite the value of timer whene v er the count source is changed. l timer 2 write contr ol if the timer 2 wr ite control bit is 0, when the v alue is wr itten in the address of timer 2, the v alue is loaded in the timer 2 and the latch at the same time . if the timer 2 wr ite control bit is 1, when the v alue is wr itten in the address of timer 2, the v alue is loaded only in the latch. the v alue in the latch is loaded in timer 2 after timer 2 underflo ws . l timer 2 output contr ol when the timer 2 (t out ) is output enab led, an in v ersion signal from the t out pin is output each time timer 2 underflo ws . in this case , set the por t shared with the t out pin to the output. n notes on timer 1 to timer 3 when the count source of timer 1 to 3 is changed, the timer count- ing v alue ma y be changed large because a thin pulse is gener ated in count input of timer . if timer 1 output is selected as t he count source of timer 2 or timer 3, when timer 1 is wr itten, the counting v alue of timer 2 or timer 3 ma y be changed large because a thin pulse is gener ated in timer 1 output. theref ore , set the v alue of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 20 structure of timer 123 mode register t out output active edge switch bit 0 : start at h output 1 : start at l output t out / f output control bit 0 : t out / f output disabled 1 : t out / f output enabled timer 2 write control bit 0 : write data in latch and counter 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (return 0 when read) timer 123 mode register (t123m :address 0029 16 ) note : internal clock f is x cin /2 in the low-speed mode. b7 b0 25 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group serial i/o serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 can be selected by setting the mode selection bit of the serial i/o1 control register to 1. for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer registers. fig. 21 block diagram of clock synchronous serial i/o1 fig. 22 operation of clock synchronous serial i/o1 function p4 6 /s clk p4 7 /s rdy1 p4 4 /r x d p4 5 /t x d f(x in ) 1/4 1/4 f/f serial i/o1 status register serial i/o1 control register receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector data bus address 0018 16 shift clock transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit buffer register transmit shift register (f(x cin ) in low-speed mode) receive enable signal s rdy1 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output t x d serial input r x d write signal to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer register has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of t he serial i/o1 control register. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 26 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers f(x in ) 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 stdetector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 control register p4 6 /s clk serial i/o status register p4 4 /r x d p4 5 /t x d (f(x cin ) in low-speed mode) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o mode selection bit of the serial i/o1 control register to 0. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 23 block diagram of uart serial i/o1 fig. 24 operation of uart serial i/o1 function tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 ] st d 0 d 1 sp d 0 d 1 st sp transmit buffer write signal ] generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1 : error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2 : the transmit interrupt (ti) can be selected to occur when either the tbe or tsc flag becomes ??by the setting of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3 : the receive interrupt (ri) is set when the rbf flag becomes ?? 4 : after data is written to the transmit buffer register when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes serial output t x d serial input r x d receive buffer read signal transmit or receive clock 27 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group [transmit buffer/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write-only and the receive buffer register is read-only. if a charac- ter bit length is 7 bits, the msb of data stored in the receive buffer register is 0. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se. writ- ing 0 to the serial i/o1 enable bit (sioe) also clears all the status flags, including the error flags. all bits of the serial i/o1 status register are initialized to 0 at re- set, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1, the transmit shift register shift comple- tion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register contains eight control bits for the serial i/o1 function. [uart control register (uartcon) ]001b 16 this is a 5 bit register containing four control bits, which are valid when uart is selected and set the data format of an data re- ceiver/transfer, and one control bit, which is always valid and sets the output structure of the p4 5 /t x d pin. [baud rate generator(brg)] 0016 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. 28 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 25 structure of serial i/o1 control registers brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as ordinary i/o pin. 1: p4 7 pin operates as s rdy1 output pin. transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 ?4 7 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p4 4 ?4 7 operate as serial i/o pins) serial i/o1 control register (sio1con : address 001a 16 ) b7 b0 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift register shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: oe u pe u fe =0 1: oe u pe u fe =1 not used (returns ??when read) serial i/o1 status register (sio1sts : address 0019 16 ) b7 b0 uart control register (uartcon : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (return ??when read) b7 b0 29 single-chip 8-bit cmos microcomputer mitsubishi mic r ocomputers 3827 g r oup s er ial i/o2 the se r ial i/o2 function can be used only f or clo c k synchronous se r ial i/ o . for clo c k synchronous se r ial i/o2 the t r ansmitter and the receiver m ust use the same clo c k . when the inte r nal clo c k is used, t r ans f er is sta r ted b y a w r ite signal to the se r ial i/o2 registe r . when an internal clock is selected as the synchronous clo c k of the serial i/o2, either p 6 2 or p 6 3 can be selected as an output pin of the synchronous clo c k . in this case, the pin that is not selected as an output pin of the synchronous clock functions as a port. [serial i/o2 control register (sio2con)] 001d 16 the se r ial i/o2 control register contains 8 bits which control v a r i - ous se r ial i/o2 functions. fig. 26 structure of serial i/o2 control register serial i/o2 control register (sio2con : address 001d 16 ) b7 internal synchronous clock select bits 0 0 0: f(x in )/8 (f(x cin )/8 in low-speed mode) 0 0 1: f(x in )/16 (f(x cin )/16 in low-speed mode) 0 1 0: f(x in )/32 (f(x cin )/32 in low-speed mode) 0 1 1: f(x in )/64 (f(x cin )/64 in low-speed mode) 1 0 0: 1 0 1: 1 1 0: f(x in )/128 (f(x cin )/128 in low-speed mode) 1 1 1: f(x in )/256 (f(x cin )/256 in low-speed mode) serial i/o2 port selection bit 0: i/o port 1: s out2 ,s clk21 /s clk22 signal output p6 1 /s out2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) transfer direction selection bit 0: lsb first 1: msb first synchronous clock selection bit 0: external clock 1: internal clock synchronous clock output pin selection bit 0: s clk21 1: s clk22 b0 b2 b1 b0 do not set fig. 27 block diagram of serial i/o2 function f( x i n ) ? ? ? ? ? ? s clk2 (note) 1/8 1/16 1/32 1/64 1/128 1/256 data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o counter 2 (3) serial i/o shift register 2 (8) synchronous circuit synchronous clock selection bit external clock internal synchronous clock select bits divider p6 3 latch p 6 3 /s clk22 p 6 2 /s clk21 p 6 1 /s out2 p6 0 /s in2 p6 2 latch p6 1 latch (note) note : it is selected by the synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial i/o port selection bit. (f(x ci n ) in low-speed mode) 30 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 28 timing of serial i/o2 function d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) serial i/o2 output s out2 serial i/o2 input s in2 serial i/o2 register write signal (note 2) serial i/o2 interrupt request bit set 1: when the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the seria l i/o2 control register. 2: when the internal clock is selected as the transfer clock, the s out2 pin goes to high impedance after transfer completion. when the external clock is selected as the transfer clock, a content of the serial i/o shift register is continued to shift during inputting a transfer clock. the s out2 pin does not go to high impedance after transfer completion. notes 31 single-chip 8-bit cmos microcomputer mitsubishi micr ocomputers 3827 gr oup pulse width modula tion (pwm) the 3827 g roup has a pwm function with an 8-bit resolution, based on a signal that is the clock input x in or that cloc k input di- vided b y 2. data setting the pwm output pin also functions as por ts p5 0 and p5 1 . set the pwm per iod b y the pwm prescaler , and set the per iod dur ing which the output pulse is an h b y the pwm register. if pwm count source is f(x in ) and the v alue in the pwm prescaler is n and the v alue in the pwm register is m (where n = 0 to 255 and m = 0 to 255) : pwm per iod = 255 5 (n+1)/f(x in ) = 51 5 (n+1) m s (when x in = 5 mhz) output pulse h per iod = pwm per iod 5 m/255 = 0.2 5 (n+1) 5 m m s (when x in = 5 mhz) pwm operation when at least either bit 1 (pwm 0 output enab le bit) or bit 2 (pwm 1 output enab le bit) of the pwm control register is set to 1, oper a- tion star ts by initializing the pwm output circuit, and pulses are output starting at an h. when one pwm output is enab led and that the other pwm output is enab led, pwm output which is en- ab led to output later star ts pulse output from halfw ay . when the pwm register or pwm prescaler is updated dur ing pwm output, the pulses will change in the cycle after the on e in which the change w as made . fig. 29 timing of pwm c yc le fig. 30 block diagram of pwm function 51 5 m 5 (n+1) 255 m s t = [51 5 (n+1)] m s pwm output m: contents of pwm register n : contents of pwm prescaler t : pwm cycle (when f(x in ) = 5 mhz) data bus count source selection bit 0 1 pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm circuit 1/2 x in pwm 0 enable bit port p5 6 pwm prescaler pwm 1 enable bit 32 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 32 pwm output timing when pwm register or pwm prescaler is changed fig. 31 structure of pwm control register b7 b0 pwm control register (pwmcon : address 002b 16 ) count source selection bit 0 : f(x in ) 1 : f(x in )/2 pwm 0 function enable bit 0 : pwm 0 disabled 1 : pwm 0 enabled pwm 1 function enable bit 0 : pwm 1 disabled 1 : pwm 1 enabled not used (return ??when read) t t2 c b t pwm register write signal pwm prescaler write signal (changes from ??to ??during ??period) (changes from ??to ?2?during pwm period) pwm (internal) a b t c t2 = stop pwm 0 function enable bit pwm 1 function enable bit pwm 0 output port port pwm 1 output port stop port when the contents of the pwm register or pwm prescaler have changed, the pwm output will change from the next period after the change. 33 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group a-d converter [a-d conversion register (ad)] 0035 16 the a-d conversion register is a read-only register that contains the result of an a-d conversion. during a-d conversion, do not read this register. [a-d control register (adcon)] 0034 16 the a-d control register controls the a-d conversion process. bits 0 to 2 are analog input pin selection bits. bit 3 is an a-d conver- sion completion bit and 0 during a-d conversion, then changes to 1 when the a-d conversion is completed. writing 0 to this bit starts the a-d conversion. bit 4 controls the transistor which breaks the through current of the resistor ladder. when bit 5, which is the ad external trigger valid bit, is set to 1, a-d conversion is started even by a rising edge or falling edge of an adt input. set ports which share with adt pins to input when using an a-d exter- nal trigger. [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref , and outputs the divided voltages. [channel selector] the channel selector selects one of the input ports p6 7 /an 7 Cp6 0 / an 0, and inputs it to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1. note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500 khz during a-d conversion. use a clock divided the main clock x in as the internal clock f . fig. 34 a-d converter block diagram fig. 33 structure of a-d control register a-d control register (adcon : address 0031 16 ) analog input pin selection bits 0 0 0 : p6 0 /s in2 /an 0 0 0 1 : p6 1 /s out2 /an 1 0 1 0 : p6 2 /s clk21 /an 2 0 1 1 : p6 3 /s clk22 /an 3 1 0 0 : p6 4 /an 4 1 0 1 : p6 5 /an 5 1 1 0 : p6 6 /an 6 1 1 1 : p6 7 /an 7 ad conversion completion bit 0 : conversion in progress 1 : conversion completed v ref input switch bit 0 : off 1 : on ad external trigger valid bit 0 : a-d external trigger invalid 1 : a-d external trigger valid interrupt source selection bit 0 : interrupt request at a-d conversion completed 1 : interrupt request at adt input rising or falling reference voltage input selection bit 0 : v ref 1 : p5 6 /da 1 b7 b0 b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 b9 b8 b7 b0 b7 b6 b5 b4 b3 b2 8-bit read (read only address 0032 16 .) (address 0032 16 ) 10-bit read (read address 0033 16 first.) (address 0033 16 ) (address 0032 16 ) note: high-order 6 bits of address 0033 16 becomes ??at reading. b1 b0 data bus a-d control register a-d conversion register resistor ladder av ss comparater adt/a-d interrupt request b7 b0 a-d control register 3 p6 0 /s in2 /an 0 p6 1 /s out2 /an 1 p6 2 /s clk21 /an 2 p6 3 /s clk22 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 10 p4 0 /adt v ref a-d conversion register (h) (l) p5 6 /da 1 channel selector 34 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers d-a converter the 3827 group has an on-chip d-a converter with 8-bit resolution and 2 channels (dai (i=1, 2)). the d-a converter is performed by setting the value in the d-a conversion register. the result of d-a converter is output from dai pin. when using the d-a converter, the corresponding port direction register bit (p5 6 /da 1 , p5 7 /da 2 ) should be set to 0 (input status). the output analog voltage v is determined by the value n (base 10) in the d-a conversion register as follows: v=v ref 5 n/256 (n=0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , the dai output enable bits are cleared to 0, and dai pin goes to high impedance state. the da output is not buffered, so connect an external buffer when driving a low-impedance load. fig. 35 structure of d-a control register fig. 36 block diagram of d-a converter fig. 37 a-d converter, d-a converter block diagram da 1 output enable bit/da 1 v ref on/off switch da 2 output enable bit/da 2 v ref on/off switch not used (return ??when read) 0 : output disabled/off 1 : output enabled/on b7 b0 d-a control register (dacon : address 0036 16 ) d-a1 conversion register (0034 16 ) d-a2 conversion register (0035 16 ) p5 6 /da 1 p5 7 /da 2 data bus d-a i conversion register (8) r-2r resistor ladder da i output enable bit v ref resistor ladder a-d conversion register (10 bits) d-a1 conversion register (8 bits) d-a2 conversion register (8 bits) r-2r resistor ladder r-2r resistor ladder d-a2 output d-a1 output (p5 6 ) (p5 7 ) d-a2 output enable switch d-a1 output enable switch v ref input on/off switch internal: d-a output external: v ref reference voltage input select switch d-a1 v ref on/off switch d-a2 v ref on/off switch 35 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group lcd drive control circuit the 3827 group has the built-in liquid crystal display (lcd) drive control circuit consisting of the following. l lcd display ram l segment output enable register l lcd mode register l voltage multiplier l selector l timing controller l common driver l segment driver l bias control circuit a maximum of 40 segment output pins and 4 common output pins can be used. fig. 38 structure of lcd mode register up to 160 pixels can be controlled for lcd display. when the lcd enable bit is set to 1 after data is set in the lcd mode register, the segment output enable register and the lcd display ram, the lcd drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and displays the data on the lcd panel. table 7 maximum number of display pixels at each duty ratio duty ratio maximum number of display pixel 80 dots or 8 segment lcd 10 digits 120 dots or 8 segment lcd 15 digits 160 dots or 8 segment lcd 20 digits 2 3 4 segment output enable bit 0 0 : output ports p3 0 ?3 5 1 : segment output seg 18 ?eg 23 segment output enable bit 1 0 : output ports p3 6 , p3 7 1 : segment output seg 24 ,seg 25 segment output enable bit 2 0 : i/o ports p0 0 ?0 5 1 : segment output seg 26 ?eg 31 segment output enable bit 3 0 : i/o ports p0 6 ,p0 7 1 : segment output seg 32 ,seg 33 segment output enable bit 4 0 : i/o port p1 0 1 : segment output seg 34 segment output enable bit 5 0 : i/o ports p1 1 ?1 5 1 : segment output seg 35 ?eg 39 lcd output enable bit 0 : disable 1 : enable not used (return ??when read) (do not write ??to this bit) segment output enable register (seg : address 0038 16 ) b7 b0 lcd mode register (lm : address 0039 16 ) duty ratio selection bits 0 0 : not used 0 1 : 2 duty (use com 0 , com 1 ) 1 0 : 3 duty (use com 0 ?om 2 ) 1 1 : 4 duty (use com 0 ?om 3 ) bias control bit 0 : 1/3 bias 1 : 1/2 bias lcd enable bit 0 : lcd off 1 : lcd on voltage multiplier control bit 0 : voltage multiplier disabled 1 : voltage multiplier enabled lcd circuit divider division ratio selection bits 0 0 : 1 division of clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input lcdck count source selection bit (note) 0 : f(x cin )/32 1 : f(x in )/8192 (f(x cin )/8192 in low-speed mode) note : lcdck is a clock for a lcd timing controller. b7 b0 36 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 39 block diagram of lcd controller/driver data bus timing controller lcd divider f(x in )/8192 f(x cin )/32 com 0 com 1 com 2 com 3 v ss v l1 v l2 v l3 seg 3 seg 2 seg 1 seg 0 address 0040 16 address 0041 16 0 1 lcdck lcdck count source selection bit lcd circuit divider division ratio selection bits bias control bit lcd enable bit duty ratio selection bits 2 2 selector selector selector selector selector selector lcd display ram address 0053 16 p1 4 /seg 38 p3 0 /seg 18 p1 5 /seg 39 level shift level shift level shift level shift level shift level shift common driver common driver common driver common driver c 1 c 2 voltage multiplier control bit level shift level shift level shift level shift segment driver segment driver segment driver segment driver segment driver segment driver bias control lcd output enable bit v cc (f(x cin )/8192 in low-speed mode) 37 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group voltage multiplier (3 times) the voltage multiplier performs threefold boosting. this circuit in- puts a reference voltage for boosting from lcd power input pin v l1 . (however, when using a 1/2 bias, connect v l1 and v l2 and apply voltage by external resistor division.) set each bit of the segment output enable register and the lcd mode register in the following order for operating the voltage mul- tiplier. 1. set the segment output enable bits (bits 0 to 5) of the seg- ment output enable register to 0 or 1. 2. set the duty ratio selection bits (bits 0 and 1), the bias con- trol bit (bit 2), the lcd circuit divider division ratio selection bits (bits 5 and 6), and the lcdck count source selection bit (bit 7) of the lcd mode register to 0 or 1. 3. set the lcd output enable bit (bit 6) of the segment output enable register to 1. 4. set the voltage multiplier control bit (bit 4) of the lcd mode register to 1. when voltage is input to the v l1 pin during operating the voltage multiplier, voltage that is twice as large as v l1 occurs at the v l2 pin, and voltage that is three times as large as v l1 occurs at the v l3 pin. when using the voltage multiplier, apply 1.3 v voltage 2.3 v to the v l1 pin. when not using the voltage multiplier,apply proper voltage to the lcd power input pins (v l1 Cv l3 ). then set the lcd output enable bit to 1. when the lcd output enable bit is set to 0, the v cc voltage is applied to the v l3 pin inside of this microcomputer. the voltage multiplier control bit (bit 4 of the lcd mode register) controls the voltage multiplier. fig. 40 example of circuit at each bias table 8 bias control and applied voltage to v l1 Cv l3 bias value 1/3 bias voltage value v l3 =v lcd v l2 =2/3 v lcd v l1 =1/3 v lcd note 1: v lcd is the maximum value of supplied voltage for the lcd panel. bias control and applied voltage to lcd power input pins to the lcd power input pins (v l1 Cv l3 ), apply the voltage shown in table 8 according to the bias value. select a bias value by the bias control bit (bit 2 of the lcd mode register). 1/2 bias v l3 =v lcd v l2 =v l1 =1/2 v lcd v l3 v l2 c 2 c 1 v l1 1/3 bias when using the voltage multiplier v l3 v l2 c 2 c 1 v l1 1/3 bias when not using the voltage multiplier open open r2 r1 r3 r1=r2=r3 contrast control v l3 v l2 c 2 c 1 v l1 1/2 bias open open r4 r5 r4=r5 contrast control v cc v cc px x 38 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers common pin and duty ratio control the common pins (com 0 Ccom 3 ) to be used are determined by duty ratio. select duty ratio by the duty ratio selection bits (bits 0 and 1 of the lcd mode register). when releasing from reset, the v cc (v l3 ) voltage is output from the common pins. table 9 duty ratio control and common pins used duty ratio common pins used notes1: com 2 and com 3 are open. 2: com 3 is open. bit 1 bit 0 com 0 , com 1 (note 1) duty ratio selection bit 2 3 4 0 1 1 1 0 1 com 0 Ccom 2 (note 2) com 0 Ccom 3 segment signal output pin segment signal output pins are classified into the segment-only pins (seg 0 Cseg 17 ), the segment/output port pins (seg 18 C seg 25 ), and the segment/i/o port pins (seg 26 Cseg 39 ). segment signals are output according to the bit data of the lcd ram corresponding to the duty ratio. after reset release, a v cc (=v l3 ) voltage is output to the segment-only pins and the seg- ment/output port pins are pulled up to the v cc (=v l3 ) voltage in the high impedance condition. the segment/i/o port pins are set to input ports, and v cc (=v l3 ) is applied to them by pull-up resis- tor. lcd display ram address 0040 16 to 0053 16 is the designated ram for the lcd dis- play. when 1 are written to these addresses, the corresponding segments of the lcd display panel are turned on. lcd drive timing the lcdck timing frequency (lcd drive timing) is generated in- ternally and the frame frequency can be determined with the following equation; f(lcdck) = frame frequency = fig. 41 lcd display ram map (frequency of count source for lcdck) (divider division ratio for lcd) f(lcdck) (duty ratio) bit address 76 5432 10 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 seg 1 seg 3 seg 5 seg 7 seg 9 seg 0 seg 2 seg 4 seg 6 seg 8 seg 10 com 3 com 2 com 1 com 0 seg 12 seg 14 seg 16 seg 18 seg 20 seg 22 seg 24 seg 26 seg 28 seg 30 seg 32 seg 34 seg 36 seg 38 seg 21 seg 23 seg 25 seg 27 seg 11 seg 13 seg 15 seg 17 seg 19 seg 29 seg 31 seg 33 seg 35 seg 37 seg 39 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 com 3 com 2 com 1 com 0 39 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group fig. 42 lcd drive waveform (1/2 bias) internal signal lcdck timing 1/4 duty voltage level v l3 v l2 =v l1 v ss v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty v l3 v l2 =v l1 v ss v l3 v ss off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 v l3 v l2 =v l1 v ss v l3 v ss off on off on off on off on com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 40 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 43 lcd drive waveform (1/3 bias) internal signal lcdck timing 1/4 duty voltage level v l3 v ss com 0 com 1 com 2 com 3 seg 0 off on off on com 3 com 2 com 1 com 0 com 3 com 2 com 1 com 0 1/3 duty off on on off on off 1/2 duty com 0 com 1 com 2 seg 0 com 0 com 1 seg 0 off on off on off on off on v l3 v l2 v ss v l1 v l3 v l2 v ss v l1 v l3 v ss v l3 v l2 v ss v l1 v l3 v ss com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 2 com 1 com 0 com 1 com 0 com 1 com 0 com 1 com 0 41 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software runaway). the watchdog timer consists of an 8-bit watchdog timer l and a 6- bit watchdog timer h. at reset or writing to the watchdog timer control register (address 0037 16 ), the watchdog timer is set to 3fff 16 . when any data is not written to the watchdog timer con- trol register (address 0037 16 ) after reset, the watchdog timer is in stop state. the watchdog timer starts to count down from 3fff 16 by writing an optional value into the watchdog timer control regis- ter (address 0037 16 ) and an internal reset occurs at an underflow. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0037 16 ) may be started before an underflow. the watchdog timer does not function when an optional value have not written to the watchdog timer control register (address 0037 16 ). when address 0037 16 is read, the following values are read: l value of high-order 6-bit counter l value of stp instruction disable bit l value of count source selection bit. when bit 6 of the watchdog timer control register (address 0037 16 ) is set to 0, the stp instruction is valid. the stp instruction is dis- abled by rewriting this bit to 1. at this time, if the stp instruction is executed, it is processed as an undefined instruction, so that a reset occurs inside. this bit cannot be rewritten to 0 by programming. this bit is 0 immediately after reset. the count source of the watchdog timer becomes the system clock f divided by 8. the detection time in this case is set to 8.19 s at x cin = 32 khz and 65.536 ms at x in = 4 mhz. however, count source of high-order 6-bit timer can be connected to a signal divided system clock by 8 directly by writing the bit 7 of the watchdog timer control register (address 0037 16 ) to 1. the detection time in this case is set to 32 ms at x cin = 32 khz and 256 m s at x in = 4 mhz. there is no difference in the detection time between the middle-speed mode and the high-speed mode. fig. 44 block diagram of watchdog timer fig. 45 structure of watchdog timer control register fig. 46 timing of reset output x in data bus x cin 1 0 internal system clock selection bit 0 1 1/16 watchdog timer h (6) watchdog timer count source selection bit reset circuit undefined instruction reset 3f 16 is set when watchdog timer is written to. internal reset reset in reset release time wait watchdog timer l (8) ff 16 is set when watchdog timer is written to. stp instruction stp instruction disable bit watchdog timer h (for read-out of high-order 6 bit) 3fff 16 is set to the watchdog timer by writing values to this address. watchdog timer h count source selection bit 0 : internal system clock/2048 (f(x in )/4096) 1 : internal system clock/8 (f(x in )/16) stp instruction disable bit 0 stp instruction enabled 1 : stp instruction disabled b7 watchdog timer register (address 0037 16 ) wdtcon b0 internal reset signal watchdog timer detection 2 ms (f(x in ) = 4mh z ) f(x in) 42 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers t out / f clock output function the internal system clock f or timer 2 divided by 2 (t out output) can be output from port p4 3 by setting the t out / f output control bit (bit 1) of the timer 123 mode register and the t out / f output control register. set bit 3 of the port p4 direction register to 1 when outputting the clock. fig. 47 structure of t out / f output-related register t out / f output control bit 0 : f clock output 1 : t out output not used (return ??when read) t out / f output control register (ckout : address 002a 16 ) b7 b0 timer 123 mode register (t123m : address 0029 16 ) t out output active edge switch bit 0 : start on ??output 1 : start on ??output t out / f output control bit 0 : t out / f output disable 1 : t out / f output enable timer 2 write control bit 0 : write data in latch and timer 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode ] ) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode ] ) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode ] ) 1 : f(x cin ) not used (return ??when read) ] : internal clock f is f(x cin )/2 in low-speed mode. b7 b0 43 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 m s or more. then the reset pin is returned to an h level (the power source voltage should be between v cc (min.) and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address con- tained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is less than 0.2 v cc for v cc of v cc (min.). fig. 48 reset circuit example fig. 49 reset sequence (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; v cc =v cc (min.) reset internal reset address data sync f x in fffc fffd ad h, ad l ad l ad h ???? x in : about 8200 cycles notes 1: the frequency relation of f(x in ) and f( f ) is f(x in ) = 8 ?f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. reset address from vector table 44 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 50 initial status at reset address (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) port p0 direction register port p1 direction register port p2 direction register port p3 output control register port p4 direction register port p5 direction register port p6 direction register port p7 direction register key input control register pull register a pull register b serial i/o1 status register serial i/o1 control register uart control register serial i/o2 control register timer x (low-order) timer x (high-order) timer y (low-order) timer y (high-order) timer 1 timer 2 timer 3 timer x mode register timer y mode register timer 123 mode register t out / f output control register pwm control register 0001 16 0003 16 0005 16 0007 16 0009 16 000b 16 000d 16 000f 16 0015 16 0016 16 0017 16 0019 16 001a 16 001b 16 001d 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 register contents address note: the contents of all other register and ram are undefined after reset, so they must be initialized by software. 5 : undefined register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 3f 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 ff 16 01 16 ff 16 00 16 00 16 00 16 00 16 00 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pc h ) (pc l ) a-d control register a-d conversion register (low-order) a-d conversion register (high-order) d-a1 conversion register d-a2 conversion register d-a control register watchdog timer control register segment output enable register lcd mode register interrupt edge selection register cpu mode register interrupt request register 1 interrupt request register 2 interrupt control register 1 interrupt control register 2 processor status register program counter watchdog timer (high-order) watchdog timer (low-order) contents of address fffd 16 contents of address fffc 16 08 16 xx 16 xx 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 3f 16 ff 16 5 5 5 5 5 5 5 1 10000000 11100000 00111111 01001000 45 single-chip 8-bit cmos microcomputer mitsubishi micr ocomputers 3827 gr oup clock genera ting circuit the 3827 g roup has tw o b uilt-in oscillation circuits . an oscillation circuit can be f or med b y connecting a resonator betw een x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator man uf acturer's recommended v alues . no exter- nal resistor is needed between x in and x out since a feed-back resistor e xists on-chip . ho w e v er , an e xter nal f eed-bac k resistor is needed betw een x cin and x cout . t o supply a cloc k signal e xter nally , input it to the x in pin and mak e the x out pin open. the sub-clock x cin -x cout oscillation circuit cannot directly input cloc ks that are e xter nally gener ated. accord- ingly , be sure to cause an e xter nal resonator to oscillate . immediately after poweron, only the x in oscillation circuit star ts oscillating, and x cin and x cout pins go to high impedance state . frequency control (1) middle-speed mode the inter nal cloc k f is the frequency of x in divided b y 8. after reset, this mode is selected. (2) high-speed mode the inter nal cloc k f is half the frequency of x in . (3) low-speed mode l the inter nal cloc k f is half the frequency of x cin . l a lo w-po w er consumption operation can be realiz ed b y stopping the main cloc k x in in this mode . t o stop the main cloc k, set bit 5 of the cpu mode register to 1. when the main cloc k x in is restar ted, set enough time f or oscil- lation to stabiliz e b y prog r amming. note: if you switch the mode between middle/high-speed and low- speed, stabiliz e both x in and x cin oscillations . the sufficient time is required f or the sub-cloc k to stabiliz e , es- pecially immediately after poweron and at returning from stop mode. when switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(x in )>3f(x cin ). fig. 51 ceramic resonator circuit fig. 52 external clock input circuit oscillation control (1) stop mode if the stp instr uction is e x ecuted, the inter nal cloc k f stops at an h le v el, and x in and x cin oscillators stop . the v alue set to the timer latch 1 and the timer latch 2 is loaded automatically to the timer 1 and the timer 2. thus , a v alue gener ated time f or stabiliz- ing oscillation should be set to the timer 1 latch and the t imer 2 latch (low-order 8 bits f or the timer 1, high-order 8 bits f or the timer 2) bef ore e x ecuting the stp instruction. either x in or x cin divided b y 16 is input to timer 1 as count source , and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register e xcept bit 4 are cleared to 0, set the timer 1 and timer 2 interr upt enable bits to disab led (0) bef ore e x ecuting the stp instr uction. oscillator restar ts at reset or when an e xter nal interr upt is receiv ed, but the inter nal clock f is not sup- plied to the cpu until timer 2 underflows..this allows timer for the cloc k circuit oscillation to stabiliz e. (2) wait mode if the wit instr uction is e x ecuted, the inter nal cloc k f stops at an h le v el. the states of x in and x cin are the same as the state be- f ore the e x ecuting the wit instruction. the internal cloc k restarts at reset or when an interr upt is received. since the oscillator does not stop , nor mal oper ation can be star ted immediately after the cloc k is restar ted. x cin x cout x in x out c in c out c cin c cout rf rd x in x out external oscillation circuit open v cc v ss c cin c cout rf rd x cin x cout 46 single-chip 8-bit cmos microcomputer 3827 gr oup mitsubishi micr ocomputers fig. 53 clock generating circuit block diagram wit instruction stp instruction timing f (internal clock) s r q stp instruction s r q main clock stop bit s r q timer 2 timer 1 1/2 1/4 x in x out x cout x cin interrupt request reset timer 1 count source selection bit timer 2 count source selection bit low-speed mode middle-/high-speed mode internal system clock selection bit (note) middle-speed mode high-speed mode or low-speed mode note: when selecting the x c oscillation, set the port x c switch bit to 1 . main clock division ratio selection bit 0 1 1 0 1 0 interrupt disable flag i 1/2 1 0 47 single-chip 8-bit cmos microcomputer mitsubishi micr ocomputers 3827 gr oup fig. 54 state transitions of system clock low-power dissipation mode (f( f ) =16 khz) notes 1 : switch the mode by the allows shown between the mode blocks . (do not switch between the mode directly without an allow. ) 2 : the all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or t he wait mode is ended. 3 : timer and lcd operate in the wait mode. 4 : when the stop mode is ended, wait time can be set by connec ting timer 1 and timer 2 in middle-/high-speed mode. 5 : when the stop mode is ended, wait time can be set by connec ting timer 1 and timer 2 in low-speed mode. 6 : wait until oscillation stabilizes after oscillating the mai n clock x in before the switching from the low-speed mode to middle-/hig h-speed mode. 7 : the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. cm 4 : port xc switch bit 0: i/o port function 1: x cin ex cout oscillating function cm 5 : main clock (x in ex out ) stop bit 0: oscillating 1: stopped cm 6 : main clock division ratio selection bit 0: f(x in )/2 (high-speed mode) 1: f(x in )/8 (middle-speed mode) cm 7 : internal system clock selection bit 0: x in ex out selected (middle-/high-speed mode) 1: x cin ex cout selected (low-speed mode) cpu mode register (cpum : address 003b 16 ) b7 b4 reset cm 6 0 1 cm 4 0 1 cm 7 =0(8 mhz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) middle-speed mode (f( f ) =1 mhz) cm 7 =0(8 mhz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) middle-speed mode (f( f ) =1 mhz) cm 7 =0(8 mhz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =0(32 khz stopped) high-speed mode (f( f ) =4 mhz) cm 7 =0(8 mhz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) high-speed mode (f( f ) =4 mhz) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =0(8 mhz oscillating) cm 4 =1(32 khz oscillating) low-speed mode (f( f ) =16 khz) low-power dissipation mode (f( f ) =16 khz) cm 7 =1(32 khz selected) cm 6 =1(middle-speed) cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) cm 7 =1(32 khz selected) cm 6 =0(high-speed) cm 5 =1(8 mhz stopped) cm 4 =1(32 khz oscillating) cm 6 0 1 cm 6 0 1 cm 6 0 1 cm 4 0 1 cm 7 0 1 cm 7 0 1 cm 5 0 1 cm 5 0 1 cm 4 cm 6 0 1 0 1 cm 4 cm 6 0 1 1 0 cm 5 cm 6 0 1 0 1 cm 5 cm 6 0 1 1 0 48 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupt the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before performing a bbc or bbs instruction. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). multiplication and division instructions the index mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. the execution of these instructions does not change the contents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instruction (ror, clb, or seb, etc.) to a direction register use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o in clock synchronous serial i/o, if the receive side is using an ex- ternal clock and it is to output the s rdy signal, set the transmit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin after transmission is completed. in serial i/o2, the s out2 pin goes to high impedance state after transmission is completed. a-d converter the comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. make sure that f(x in ) is at least 500 khz during an a-d conver- sion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency. 49 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group data required for mask orders the following are necessary when ordering a mask rom produc- tion: (1) mask rom order confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical copies) data required for rom writing or- ders the following are necessary when ordering a rom writing: (1) rom writing confirmation form (2) mark specification form (3) data to be written to rom, in eprom form (three identical copies) rom programming method the built-in prom of the blank one time prom version and built- in eprom version can be read or programmed with a general-purpose prom programmer using a special programming adapter. set the address of prom programmer in the user rom area. fig. 55 programming and testing of one time prom version package 100pfb-a 100p6q-a 100p6s-a 100d0 name of programming adapter under development (pca4738h-100a) pca4738g-100a pca4738f-100a pca4738l-100a table 10 special programming adapter the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 55 is recommended to verify programming. programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : 50 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers v v h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 Cp5 3 , p5 6 , p6 1 , p6 4 Cp6 7 , p7 1 Cp7 7 h input voltage p2 0 Cp2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p4 0 , p4 3 , p4 5 , p4 7 , p5 0 Cp5 3 , p5 6 , p6 1 , p6 4 Cp6 7 , p7 1 Cp7 7 l input voltage p2 0 Cp2 7 , p4 1 , p4 2 , p4 4 , p4 6 , p5 4 , p5 5 , p5 7 , p6 0 , p6 2 , p6 3 , p7 0 reset x in electrical characteristics absolute maximum ratings table 11 absolute maximum ratings recommended operating conditions table 12 recommended operating conditions (v cc = 2.5 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) power source voltage a-d, d-a conversion reference voltage analog power source voltage analog input voltage an 0 Can 7 5.5 5.5 5.5 v cc +0.3 v cc v cc v ss v ref av ss v ia symbol parameter limits min. v v v v v unit 4.0 2.2 2.2 2.7 av ss 5.0 5.0 5.0 0 0 typ. max. power source voltage v o v o v o v o pd topr tstg C0.3 to 7.0 v power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 input voltage p4 0 , p7 1 Cp7 7 input voltage p7 0 input voltage v l1 input voltage v l2 input voltage v l3 input voltage c 1 , c 2 input voltage reset, x in output voltage c 1 , c 2 v cc v i symbol parameter conditions ratings unit all voltages are based on v ss . output transistors are cut off. v i v i v i v i v i v i v i v o v o v o output voltage p0 0 Cp0 7 , p1 0 Cp1 5 , p3 0 Cp3 7 output voltage p1 6 , p1 7 , p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 , p8 1 output voltage p4 0 , p7 1 Cp7 7 output voltage v l3 output voltage v l2 , seg 0 Cseg 17 output voltage x out power dissipation operating temperature storage temperature at output port at segment output ta = 25 c C0.3 to v cc +0.3 C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to v l2 v l1 to v l3 v l2 to 7.0 C0.3 to 7.0 C0.3 to v cc +0.3 C0.3 to 7.0 C0.3 to v cc C0.3 to v l3 C0.3 to v cc +0.3 C0.3 to 7.0 C0.3 to 7.0 C0.3 to v l3 C0.3 to v cc +0.3 300 C20 to 85 C40 to 125 v v v v v v v v v v v v v v v v mw c c high-speed mode f(x in ) = 8 mhz middle-speed mode f(x in ) = 8 mhz low-speed mode h input voltage h input voltage v ih v ih v ih v ih v il v il v il v il l input voltage l input voltage 0.7 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0 0 0 0 v cc v cc v cc v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.2 v cc v v v v v v 51 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) p4 0 , p7 1 Cp7 7 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 (note 1) p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 1) p4 0 , p7 1 Cp7 7 (note 1) p0 0 Cp0 7 , p1 0 Cp1 5 , p3 0 Cp3 7 (note 2) h peak output current p1 6 , p1 7 , p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 2) p0 0 Cp0 7 , p1 0 Cp1 5 , p3 0 Cp3 7 (note 2) l peak output current p1 6 , p1 7 , p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 2) p4 0 , p7 1 Cp7 7 (note 2) p0 0 Cp0 7 , p1 0 Cp1 5 , p3 0 Cp3 7 (note 3) p1 6 , p1 7 , p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 p0 0 Cp0 7 , p1 0 Cp1 5 , p3 0 Cp3 7 (note 3) l average output current p1 6 , p1 7 , p2 0 Cp2 7 , p4 1 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 (note 3) p4 0 , p7 1 Cp7 7 (note 3) C20 C20 20 20 80 C10 C10 10 10 40 C1.0 table 13 recommended operating conditions (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) notes1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. h total peak output current h total peak output current l total peak output current l total peak output current l total peak output current h total average output current h total average output current l total average output current l total average output current l total average output current h peak output current s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) s i ol(avg) i oh(peak) symbol parameter limits min. ma ma ma ma ma ma ma ma ma ma ma unit typ. max. l peak output current l peak output current h average output current h average output current l average output current l average output current i oh(peak) i ol(peak) i ol(peak) i ol(peak) i oh(avg) i oh(avg) i ol(avg) i ol(avg) i ol(avg) C5.0 5.0 10 20 C0.5 C2.5 2.5 5.0 10 ma ma ma ma ma ma ma ma ma 52 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers table 14 recommended operating conditions (mask rom version) (v cc = 2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) notes1: when the oscillation frequency has a duty cycle of 50%. 2: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. input frequency for timers x and y (duty cycle 50%) f(cntr 0 ) f(cntr 1 ) symbol parameter limits min. mhz unit typ. max. (4.0 v v cc 5.5 v) 32.768 4.0 main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (notes 1, 2) f(x in ) f(x cin ) (2.2 v v cc 4.0 v) high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.2 v v cc 4.0 v) middle-speed mode (10 5 v cc C4)/9 8.0 (20 5 v cc C8)/9 8.0 50 mhz mhz mhz mhz khz table 15 recommended operating conditions (prom version) (v cc = 2.5 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) notes1: when the oscillation frequency has a duty cycle of 50%. 2: when using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. input frequency for timers x and y (duty cycle 50%) f(cntr 0 ) f(cntr 1 ) symbol parameter limits min. mhz unit typ. max. (4.0 v v cc 5.5 v) 32.768 4.0 main clock input oscillation frequency (note 1) sub-clock input oscillation frequency (notes 1, 2) f(x in ) f(x cin ) (2.5 v v cc 4.0 v) high-speed mode (4.0 v v cc 5.5 v) high-speed mode (2.5 v v cc 4.0 v) middle-speed mode (2 5 v cc ) C4 8.0 (4 5 v cc ) C8 8.0 50 mhz mhz mhz mhz khz test conditions test conditions 53 single-chip 8-bit cmos microcomputer mitsubishi micr ocomputers 3827 gr oup v cc = 5.0 v , v o = v cc , pull-ups on output tr ansistors off v cc = 2.2 v , v o = v cc , pull-ups on output tr ansistors off v o = v cc , pull-ups off output tr ansistors off v o = v ss , pull-ups off output tr ansistors off i ol = 10 ma i ol = 3.0 ma i ol = 2.5 ma v cc = 2.2 v i ol = 5 ma i ol = 1.5 ma i ol = 1.25 ma v cc = 2.2 v v ol i oh = e1 ma i oh = e0.25 m a v cc = 2.2 v i oh = e5 ma i oh = e1.5 ma i oh = e1.25 ma v cc = 2.2 v v v cc e2.0 h output v oltage p0 0 ep0 7 , p1 0 ep1 5 , p3 0 ep3 7 symbol p a r ameter limits min. unit 0.5 ty p . max. t est conditions v oh 2.0 0.5 t able 16 electrical c haracteristics (v cc =4.0 to 5.5 v , t a = e20 to 85 c , unless otherwise noted) i ol = 10 ma i ol = 5 ma v cc = 2.2 v v i = v cc v i = v cc v i = v cc v i = v ss pull-ups off v cc = 5 v , v i = v ss pull-ups on v cc = 2.2 v , v i = v ss pull-ups on v i = v ss v i = v ss h output v oltage p1 6 , p1 7 , p2 0 ep2 7 , p4 1 ep4 7 , p5 0 ep5 7 , p6 0 ep6 7 (note 1) l output v oltage p0 0 ep0 7 , p1 0 ep1 5 , p3 0 ep3 7 l output v oltage p1 6 , p1 7 , p2 0 ep2 7 , p4 1 ep4 7 , p5 0 ep5 7 , p6 0 ep6 7 l output v oltage p4 0 , p7 1 ep7 7 hysteresis int 0 eint 2 , adt , cntr 0, cntr 1, p2 0 ep2 7 hysteresis s clk , r x d hysteresis reset h input current p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p4 0 ep4 7 , p5 0 ep5 7 , p6 0 ep6 7 , p7 0 ep7 7 h input current reset h input current x in l input current p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 ,p4 0 ep4 7 , p5 0 ep5 7 , p6 0 ep6 7 , p7 0 ep7 7 l input current p7 0 l input current reset l input current x in output load current p3 0 ep3 7 output leak current p3 0 ep3 7 v oh v ol v ol v t+ e v te v t+ e v te v t+ e v te i ih i ih i ih i il i il i il i leak v cc e2.0 v cc e0.5 e60.0 e5.0 e60.0 e5.0 0.5 0.5 4.0 e120.0 e20.0 e4.0 e20.0 2.0 0.5 0.5 5.0 5.0 e5.0 e240.0 e40.0 e5.0 e5.0 e240.0 e40.0 5.0 e5.0 v v v v v v v v v v m a m a m a m a m a m a m a m a m a m a i il i lo ad v cc e0.8 v cc e0.8 v v v 0.8 v 0.8 0.3 v m a m a m a e120.0 54 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers table 17 electrical characteristics (v cc =2.2 to 5.5 v, ta = C20 to 85 c, unless otherwise noted) v 5.5 ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? high-speed mode, v cc = 5 v f(x in ) = 8 mhz (in wit state) f(x cin ) = 32.768 khz output transistors off a-d converter in operating ? low-speed mode, v cc = 5 v, ta 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 5 v, ta = 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off ? low-speed mode, v cc = 3 v, ta 55 c f(x in ) = stopped f(x cin ) = 32.768 khz output transistors off ? low-speed mode, v cc = 3 v, ta 25 c f(x in ) = stopped f(x cin ) = 32.768 khz (in wit state) output transistors off all oscillation stopped (in stp state) output transistors off symbol parameter limits min. unit typ. max. ta = 25 c ta = 85 c test conditions i cc power source current 6.4 v ram ram retention voltage at clock stop mode 2.0 when using voltage multiplier v l1 = 1.8 v v l1 < 1.3 v v l1 i l1 power source voltage power source current (v l1 ) (note) note: when the voltage multiplier control bit of the lcd mode register (bit 4 at address 0039 16 ) is 1. 1.3 1.6 35 20 15.0 4.5 0.1 1.8 3.0 10.0 3.2 70 40 22.0 9.0 1.0 10.0 2.3 6.0 50.0 ma m a m a m a m a m a v ma 13 m a 55 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group table 18 a-d converter characteristics (v cc = 2.2 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, 4 mhz f(x in ) 8 mhz, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions C resolution absolute accuracy (excluding quantization error) v cc 3 v ref = 4 v v cc 3 v ref = 2.7 v 30.5 bits lsb lsb 35 10 2.5 4.0 31 (note) note: when an internal trigger is used in middle-speed mode, it is 34 m s. m s f(x in ) = 4 mhz v ref = 5 v conversion time ladder resistor reference power source input current C t conv r ladder i vref k w m a table 19 d-a converter characteristics (v cc = 2.2 to 5.5 v, v cc = v ref , v ss = av ss = 0 v, ta = C20 to 85 c, in middle/high-speed mode unless otherwise noted) symbol parameter limits min. unit typ. max. test conditions C resolution v cc = v ref = 5 v v cc = v ref = 2.7 v 1 bits % % m s k w ma 3 2.5 8 1.0 2.0 note: using one d-a converter, with the value in the d-a conversion register of the other d-a converter being 00 16 , and excluding currents flowing through the a-d resistance ladder. (note) setting time output resistor C t su r o 4 6.0 50 absolute accuracy analog port input current i ia i vref reference power source input current m a 200 5.0 150 0.5 56 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers table 20 timing requirements 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 250 105 105 80 80 800 370 370 220 100 1000 400 400 200 200 note: when bit 6 of address 001a 16 is 1. divide this value by four when bit 6 of address 001a 16 is 0. reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 2 input h pulse width int 0 to int 2 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time (note) serial i/o2 clock input h pulse width (note) serial i/o2 clock input l pulse width (note) serial i/o2 input set up time serial i/o2 input hold time t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk1 ) t wh(s clk1 ) t wl(s clk1 ) t su(r x dCs clk1 ) t h(s clk1 Cr x d) t c(s clk2 ) t wh(s clk2 ) t wl (s clk2 ) t su(s in2 Cs clk2 ) t h(s clk2 Cs in2 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit typ. max. table 21 timing requirements 2 (v cc = 2.2 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) 2 125 45 40 900/(v cc C0.4) t c(cntr) /2C20 t c(cntr) /2C20 230 230 2000 950 reset input l pulse width main clock input cycle time (x in input) main clock input h pulse width main clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 2 input h pulse width int 0 to int 2 input l pulse width serial i/o1 clock input cycle time (note) serial i/o1 clock input h pulse width (note) t w(reset) t c(x in ) t wh(x in ) t wl(x in ) t c(cntr) t wh(cntr) t wl(cntr) t wh(int) t wl(int) t c(s clk1 ) t wh(s clk1 ) symbol parameter limits min. m s ns ns ns ns ns ns ns ns ns ns unit typ. max. note: when bit 6 of address 001a 16 is 1. divide this value by four when bit 6 of address 001a 16 is 0. t su(s in2 Cs clk2 ) t h(s clk2 Cs in2 ) t wl(s clk1 ) t su(r x dCs clk1 ) t h(s clk1 Cr x d) t c(s clk2 ) t wh(s clk2 ) t wl(s clk2 ) serial i/o1 clock input l pulse width (note) serial i/o1 input set up time serial i/o1 input hold time serial i/o2 clock input cycle time (note) serial i/o2 clock input h pulse width (note) serial i/o2 clock input l pulse width (note) serial i/o2 input set up time serial i/o2 input hold time 950 400 200 2000 950 950 400 300 ns ns ns ns ns ns ns ns 57 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group table 22 switching characteristics 1 (v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) notes1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 140 30 30 0.2 5 t c (s clk2 ) 40 30 30 symbol parameter limits min. ns ns ns ns ns ns ns ns ns ns ns ns ns unit t c (s clk1 )/2C30 t c (s clk1 )/2C30 C30 10 10 ty p . max. t wh(s clk1 ) t wl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) table 23 switching characteristics 2 (v cc = 2.2 to 4.0 v, v ss = 0 v, ta = C20 to 85 c, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns unit notes1: when the p4 5 /t x d p-channel output disable bit of the uart control register (bit 4 of address 001b 16 ) is 0. 2: x out and x cout pins are excluded. serial i/o1 clock output h pulse width serial i/o1 clock output l pulse width serial i/o1 output delay time (note 1) serial i/o1 output valid time (note 1) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output h pulse width serial i/o2 clock output l pulse width serial i/o2 output delay time serial i/o2 output valid time serial i/o2 clock output falling time cmos output rising time (note 2) cmos output falling time (note 2) 350 50 50 0.2 5 t c (s clk2 ) 50 50 50 symbol parameter limits min. t c (s clk1 )/2C50 t c (s clk1 )/2C50 C30 20 20 max. t wh(s clk1 ) twl(s clk1 ) t d(s clk1 Ct x d) t v(s clk1 Ct x d) t r(s clk1 ) t f(s clk1 ) t wh(s clk2 ) t wl(s clk2 ) t d(s clk2 Cs out2 ) t v(s clk2 Cs out2 ) t f(s clk2 ) t r(cmos) t f(cmos) ty p . t c (s clk2 )/2C160 t c (s clk2 )/2C160 0 t c (s clk2 )/2C240 t c (s clk2 )/2C240 0 58 single-chip 8-bit cmos microcomputer 3827 group mitsubishi microcomputers fig. 56 circuit for measuring output switching characteristics measurement output pin 100 pf cmos output note : when bit 4 of the uart control register (address 001b 16 ) is ?? (n-channel open-drain output mode) n-channel open-drain output (note) 1 k w 100 pf measurement output pin 59 single-chip 8-bit cmos microcomputer mitsubishi microcomputers 3827 group fig. 57 timing diagram 0.2v cc t d (s clk -t x d) t f 0.2v cc 0.8v cc 0.8v cc t r t su (r x d-s clk )t h (s clk -r x d) t v (s clk -t x d) t c (s clk ) t wl (s clk ) t wh (s clk ) t x d r x d s clk 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8v cc t w (reset) reset 0.2v cc t wl (cntr) 0.8v cc t wh (cntr) t c (cntr) 0.2v cc t wl (int) 0.8v cc t wh (int) cntr 0 , cntr 1 int 0 ?nt 3 60 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-92b<85a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38277m8mxxxfp/gp/hp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38277m8m must be entered in addresses 0000 16 to 0008 16 . and set data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hesadecimal notation. (1/2) address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 2 = 32 16 7 = 37 16 7 = 37 16 m = 4d 16 8 = 38 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 m =4d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 product name: m38277m8mxxxfp m38277m8mxxxgp m38277m8mxxxhp mask rom order confirmation form in the address space of the microcomputer, the internal rom area is from address 8080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . eprom type (indicate the type used) 27512 0000 16 000f 16 0010 16 807f 16 8080 16 fffd 16 fffe 16 ffff 16 eprom address product name ascii code : m38277m8m data rom 32k-130 bytes 61 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 740 family mask rom confirmation form single-chip microcomputer m38277m8mxxxfp/gp/hp mitsubishi electric gzz-sh52-92b<85a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program because ascii codes of the product name are written to addresses 0000 16 to 0008 16 of eprom. 27512 eprom type the pseudo-command *= d $0000 .byte d m38277m8m note: if the name of the product written to the eproms does not match the name of the mask rom confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (100p6s for m38277m8mxxxfp, 100p6q for m38277m8mxxxgp, 100pfb for m38277m8mxxxhp) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = ceramic resonator external clock input quartz crystal other ( ) mhz (2) how will you use the x cin -x cout oscillator? ceramic resonator quartz crystal h 4. comments at what frequency? f(x cin ) = other ( ) mhz 62 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers rom programming confirmation form gzz-sh51-93b<85a0> receipt 740 family rom programming confirmation form single-chip microcomputer m38279ef-xxxfp/gp/hp mitsubishi electric rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce rom programming based on this data. we shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address 1080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38279ef- must be entered in addresses 0000 16 to 0008 16 . and set data ff 16 in addresses 0009 16 to 000f 16 . the ascii codes and addresses are listed to the right in hesadecimal notation. eprom type (indicate the type used) 27512 0000 16 000f 16 0010 16 107f 16 1080 16 fffd 16 fffe 16 ffff 16 eprom address product name ascii code : m38279ef- data rom 60k-130 bytes (1/2) address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 2 = 32 16 7 = 37 16 9 = 39 16 e = 45 16 f = 46 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 C =2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 product name: m38279ef-xxxfp m38279ef-xxxgp m38279ef-xxxhp 63 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 740 family rom programming confirmation form single-chip microcomputer m38279ef-xxxfp/gp/hp mitsubishi electric gzz-sh51-93b<85a0> rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program because ascii codes of the product name are written to addresses 0000 16 to 0008 16 of eprom. 27512 eprom type the pseudo-command *= d $0000 .byte d m38279ef- note: if the name of the product written to the eproms does not match the name of the rom programming confirmation form, the rom will not be processed. (2/2) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (100p6s for m38279ef-xxxfp, 100p6q for m38279ef-xxxgp, 100pfb for m38279ef-xxxhp) and attach it to the rom programming confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = ceramic resonator external clock input quartz crystal other ( ) mhz (2) how will you use the x cin -x cout oscillator? ceramic resonator quartz crystal h 4. comments at what frequency? f(x cin ) = other ( ) mhz 64 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers qfp100-p-1420-0.65 1.58 weight(g) C jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 5 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 lqfp100-p-1414-0.50 weight(g) e jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 5 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e e c h e 1 76 75 51 50 26 25 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 65 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers tqfp100-p-1212-0.40 weight(g) C jedec code eiaj package code lead material cu alloy 100pfb-a plastic 100pin 12 5 12mm body tqfp symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.15 0.1 0.225 i 2 1.0 m d 12.4 m e 12.4 8 0 0.08 1.0 0.6 0.5 0.4 14.2 14.0 13.8 14.2 14.0 13.8 0.4 12.1 12.0 11.9 12.1 12.0 11.9 0.175 0.125 0.105 0.23 0.18 0.13 1.0 0.05 1.2 e h e e d h d 1 25 75 76 100 26 50 51 f b e c l l 1 a 1 a 2 a m e b 2 l 2 m d e recommended mount pad detail f y under development weight(g) jedec code eiaj package code 100d0 glass seal 100pin qfn 31 50 81 51 80 30 1 1.075typ 0.45typ 0.65typ index 3.5typ 5.0max 0.65typ 1.075typ 0.35typ 0.65typ 12.35 0.15 15.6 0.13 21.0 0.13 18.85 0.15 100 66 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name note1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 14 characters : only 0 ~ 9, a ~ z, +, C, /, (, ), &, ? , . (periods), , (commas) are usable. 4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required 100p6s (100-pin qfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi catalog name and the special mark (if needed). a. standard mitsubishi mark c. special mark required b. customers parts number + mitsubishi catalog name mitsubishi ic catalog name note1 : if the special mark is to be printed, indicate the desired layout of the mark in the left figure. the layout will be duplicated as close as possible. mitsubishi lot number (6-digit or 7-digit) and mask rom number (3-digit) are always marked. 2 : if the customers trade mark logo must be used in the special mark, check the box below. please submit a clean original of the logo. for the new special character fonts a clean font original (ideally logo drawing) must be submitted. special logo required 1 30 31 81 50 80 51 100 mitsubishi lot number (6-digit or 7-digit) 1 30 31 81 50 80 51 100 1 30 31 81 50 80 51 100 67 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 1 76 75 51 50 26 25 100 mitsubishi lot number (6-digit or 7-digit) customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name note1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 12 characters : only 0 ~ 9, a ~ z, +, C, /, (, ), &, ? , . (periods), , (commas) are usable. 4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required 100p6q (100-pin lqfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi catalog name and the special mark (if needed). a. standard mitsubishi mark c. special mark required b. customers parts number + mitsubishi catalog name mitsubishi ic catalog name mitsubishi ic catalog name note1 : if the special mark is to be printed, indicate the desired layout of the mark in the left figure. the layout will be duplicated as close as possible. mitsubishi lot number (6-digit or 7-digit) and mask rom number (3-digit) are always marked. 2 : if the customers trade mark logo must be used in the special mark, check the box below. please submit a clean original of the logo. for the new special character fonts a clean font original (ideally logo drawing) must be submitted. special logo required mitsubishi lot number (6-digit or 7-digit) 1 76 75 51 50 26 25 100 1 76 75 51 50 26 25 100 68 3827 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers customers parts number note : the fonts and size of characters are standard mitsubishi type. mitsubishi ic catalog name note1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customers parts number can be up to 10 characters : only 0 ~ 9, a ~ z, +, C, /, (, ), &, ? , . (periods), , (commas) are usable. 4 : if the mitsubishi logo is not required, check the box below. mitsubishi logo is not required 100pfb (100-pin tqfp) mark specification form mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi catalog name and the special mark (if needed). a. standard mitsubishi mark c. special mark required b. customers parts number + mitsubishi catalog name mitsubishi ic catalog name mitsubishi ic catalog name note1 : if the special mark is to be printed, indicate the desired layout of the mark in the left figure. the layout will be duplicated as close as possible. mitsubishi lot number (6-digit or 7-digit) and mask rom number (3-digit) are always marked. 2 : if the customers trade mark logo must be used in the special mark, check the box below. please submit a clean original of the logo. for the new special character fonts a clean font original (ideally logo drawing) must be submitted. special logo required 1 25 75 76 100 26 50 51 mitsubishi lot number (6-digit or 7-digit) mitsubishi lot number (6-digit or 7-digit) 1 25 75 76 100 26 50 51 1 25 75 76 100 26 50 51 5 : the allocation of mitsubishi ic catalog name and mitsubishi product number depend on the mitsubishi ic catalog names characters, and requiring mitsubishi logo or not. ? 1998 mitsubishi electric corp. new publication, effective jun. 1998. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. rev. rev. no. date 1.0 first edition 980602 revision description list 3827 group data sheet (1/1) revision description |
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